New Hybrid Memory-Based Packet Buffer For Networking Computers
Korean researchers have developed a highly available adaptive data packet buffer for non-volatile hybrid memory used in Internet routers and switches. This technology promises to increase the guarantees of high availability of the systems, using phase-change memory to store packets in transit so that they are not lost in the event of a power failure.
Increasing the speed of data networks and the Internet itself is crucial for digital advancement, and network equipment such as routers and switches must not only increase the bandwidth they must support but must ensure maximum availability, even when power outages occur. To do this, the industry is developing products that integrate a high-speed non-volatile memory buffer to store data packets, but traditional memory technologies will soon not be fast or reliable enough.
Global internet traffic does not stop growing and there are more and more applications that demand maximum availability, and that move through public networks, so the industry is looking for new formulas, exploring emerging technologies such as phase-change memory (PCM). This memory could provide high availability in finding destinations for routers and switches, and there have been different research projects on its possible use in this field.
An example is a work recently presented by a team of researchers from a University and South Korean memory firm Samsung, who have designed a new high-availability packet buffer based on hybrid non-volatile memory. In their work, published in the journal IEEE Transactions on Very Large Scale Integration (VLSI) Systems, they explain that a packet buffer for Internet routers and switches cannot benefit from the lookup table approach because it requires a lot of memory. bigger and with higher bandwidth. This is because its memory traffic is divided equally between reads and writes, while the routing table accesses are dominated by reads.
And they consider that phase-change memory (PCM) could provide high availability, even when the system reboots, even though its write bandwidth is insufficient, so they propose using a hybrid memory-based packet buffer in Magnetic RAM (MRAM) and PCM, along with a packet mapping method. They state that with a small MRAM module and a higher capacity PCM memory, the performance of the packet buffer traditionally used in these computers, which is based on DRAM memory, can be exceeded by between 22.4% and 28.5% for the Internet mix packet traffic.
This would be achieved both when you want to optimize only the bandwidth and when you want to improve this parameter and the useful life of the memory. To achieve this, they have developed an adaptive method of mapping small packets, with dimensions less than the default packet size threshold of the MRAM, which maximizes the bandwidth of the PCM memory. This system is capable of dynamically changing the packet size threshold, significantly improving the useful life of the PCM memory that stores data packets.
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